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| IS61C632A IS61C632A 32K x 32 SYNCHRONOUS PIPELINED STATIC RAM DESCRIPTION The ICSI IS61C632A is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the i486TM, PentiumTM, 680X0TM, and PowerPCTM microprocessors. It is organized as 32,768 words by 32 bits, fabricated with ICSI's advanced CMOS technology. The device integrates a 2-bit burst counter, highspeed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3 controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61C632A and controlled by the ADV (burst address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after three cycles of the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ (or no connect) on MODE pin selects INTERLEAVED Burst. FEATURES * Fast access time: - 4 ns-125 MHZ; 5 ns-100 MHz; 6 ns-83 MHz; 7 ns-75 MHz; 8 ns-66 MHz * Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * PentiumTM or linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Common data inputs and data outputs * Power-down control by ZZ input * JEDEC 100-Pin LQFP and PQFP package * Single +3.3V power supply * Two Clock enables and one Clock disable to eliminate multiple bank bus contention. * Control pins mode upon power-up: - MODE in interleave burst mode - ZZ in normal operation mode These control pins can be connected to GNDQ or VCCQ to alter their power-up state ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. SSR001-0B 1 IS61C632A BLOCK DIAGRAM MODE Q0 A0' CLK CLK A0 BINARY COUNTER ADV ADSC ADSP CE CLR Q1 A1' A1 32K x 32 MEMORY ARRAY 13 15 A14-A0 15 D Q ADDRESS REGISTER CE CLK 32 32 GW BWE BW4 D Q DQ32-DQ25 BYTE WRITE REGISTERS CLK D BW3 Q DQ24-DQ17 BYTE WRITE REGISTERS CLK D BW2 Q DQ16-DQ9 BYTE WRITE REGISTERS CLK D BW1 Q DQ8-DQ1 BYTE WRITE REGISTERS CLK CE1 CE2 CE3 D Q 4 ENABLE REGISTER CE CLK INPUT REGISTERS CLK OUTPUT REGISTERS CLK OE 32 DATA[32:1] D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Circuit Solution Inc. SSR001-0B IS61C632A PIN CONFIGURATION 100-Pin LQFP and PQFP (Top View) A6 A7 CE1 CE2 BW4 BW3 BW2 BW1 CE3 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9 NC DQ17 DQ18 VCCQ GNDQ DQ19 DQ20 DQ21 DQ22 GNDQ VCCQ DQ23 DQ24 NC VCC NC GND DQ25 DQ26 VCCQ GNDQ DQ27 DQ28 DQ29 DQ30 GNDQ VCCQ DQ31 DQ32 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 NC NC NC DQ16 DQ15 VCCQ GNDQ DQ14 DQ13 DQ12 DQ11 GNDQ VCCQ DQ10 DQ9 GND NC VCC ZZ DQ8 DQ7 VCCQ GNDQ DQ6 DQ5 DQ4 DQ3 GNDQ VCCQ DQ2 DQ1 NC PIN DESCRIPTIONS A0-A14 CLK ADSP ADSC ADV BW1-BW4 BWE GW CE1, CE2, CE3 Address Inputs Clock Processor Address Status Controller Address Status Burst Address Advance Synchronous Byte Write Enable Byte Write Enable Global Write Enable GNDQ Synchronous Chip Enable Isolated Output Buffer Ground OE DQ1-DQ32 ZZ MODE VCC GND VCCQ Output Enable Data Input/Output Sleep Mode Burst Sequence Mode +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V Integrated Circuit Solution Inc. SSR001-0B 3 IS61C632A TRUTH TABLE OPERATION Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS USED None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 H L L L L L L L L L X X H H X H X X H H X H CE2 X L X L X H H H H H X X X X X X X X X X X X CE3 X X H X H L L L L L X X X X X X X X X X X X ADSP ADSC X L L H H L L H H H H H X X H X H H X X H X L X X L L X X L L L H H H H H H H H H H H H ADV WRITE X X X X X X X X X X L L L L L L H H H H H H X X X X X X X L H H H H H H L L H H H H L L OE X X X X X L H X L H L H L H X X L H L H X X DQ High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D Notes: 1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK). 2. Wait states are inserted by suspending burst. 3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is LOW. WRITE=H means all byte write enable signals are HIGH. 4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time. 5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock. PARTIAL TRUTH TABLE FUNCTION READ READ WRITE Byte 1 WRITE All Bytes WRITE All Bytes GW H H H X L BWE H X L L X BW1 X H L L X BW2 X H H L X BW3 BW4 X H H L X X H H L X 4 Integrated Circuit Solution Inc. SSR001-0B IS61C632A INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = GNDQ) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN Parameter Temperature Under Bias Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Value -10 to +85 -55 to +150 1.8 100 -0.5 to VCCQ + 0.3 -0.5 to 5.5 Unit C C W mA V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Circuit Solution Inc. SSR001-0B 5 IS61C632A OPERATING RANGE Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V +10%, -5% 3.3V +10%, -5% DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND VIN VCCQ(2) GND VOUT VCCQ, OE = VIH Com. Ind. Com. Ind. Test Conditions IOH = -5.0 mA IOL = 5.0 mA Min. 2.4 -- 2.0 -0.3 -5 -10 -5 -10 Max. -- 0.4 VCCQ + 0.3 0.8 5 15 10 Unit V V V V A A POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol Parameter ICC AC Operating Supply Current Test Conditions Device Selected, All Inputs = VIL or VIH OE = VIH, Cycle Time tKC min. Com. Ind. -4 Typ. Max 150 180 ---- -5 Typ. Max. 140 170 ---- -6 Typ. Max. 130 160 140 170 -7 Typ. Max. 120 150 130 160 -8 Typ. Max. Unit 110 140 mA 120 150 A ISB Standby Current Device Deselected, Com. VCC = Max., Ind. All Inputs = VIH or VIL CLK Cycle Time tKC min. Com. Ind. 15 -- 45 -- 15 -- 45 -- 15 20 45 50 15 20 45 50 15 20 45 50 mA A IZZ Power-Down Mode ZZ = VCCQ, CLK Running Current All Inputs GND + 0.2V or VCC - 0.2V 1 -- 10 -- 1 -- 10 -- 1 2 10 20 1 2 10 20 1 2 10 20 mA mA Note: 1. MODE pin has an internal pull-up. ZZ pin has an internal pull-down. These pins may be a No Connect, tied to GND, or tied to VCCQ. 2. MODE pin should be tied to Vcc or GND. They exhibit 10 A maximum leakage current when tied to GND + 0.2V or Vcc - 0.2V. 6 Integrated Circuit Solution Inc. SSR001-0B IS61C632A CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 2.5V ZO = 50 OUTPUT Output Buffer 30 pF 50 5 pF Including jig and scope 351 1.25V Figure 1 Figure 2 Integrated Circuit Solution Inc. SSR001-0B 7 IS61C632A READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter tKC tKH tKL tKQ tKQX (2) (2,3) -4 Min. Max. 8 4 4 -- 1.5 0 1.5 -- 0 0 -- 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 25 -- -- -- 4 -- -- 4 4 -- -- 4.5 -- -- -- -- -- -- -- -- -- -- -- -5 Min. Max. 10 4 4 -- 1.5 0 1.5 -- 0 0 -- 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 35 -- -- -- 5 -- -- 5 5 -- -- 4.8 -- -- -- -- -- -- -- -- -- -- -- -6 Min. Max. 12 4 4 -- 2 0 2 -- 0 0 -- 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 45 -- -- -- 6 -- -- 6 6 -- -- 6 -- -- -- -- -- -- -- -- -- -- -- -7 Min. Max. 13 6 6 -- 2 0 2 -- 0 0 -- 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 -- -- -- 7 -- -- 6 6 -- -- 6 -- -- -- -- -- -- -- -- -- -- -8 Min. Max. Unit 15 6 6 -- 2 0 2 -- 0 0 -- 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 80 -- -- -- 8 -- -- 6 6 -- -- 6 -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z tKQLZ tKQHZ(2,3) Clock High to Output High-Z tOEQ tOEQX tOELZ (2) Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z (2,3) tOEHZ(2,3) Output Disable to Output High-Z tAS tSS tWS tCES tAVS tAH tSH tWH tCEH tAVH tCFG Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Configuration Setup (1) 66.7 -- Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with the load in Figure 2. 8 Integrated Circuit Solution Inc. SSR001-0B IS61C632A READ CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP tSS tSH ADSC initiate read ADSC tAVS tAVH Suspend Burst ADV tAS tAH A14-A0 RD1 tWS tWH RD2 RD3 GW tWS tWH BWE BW4-BW1 tCES tCEH CE1 Masks ADSP CE1 tCES tCEH CE2 and CE3 only sampled with ADSP or ADSC Unselected with CE2 CE2 tCES tCEH CE3 tOEQ tOEHZ OE tOELZ tOEQX tKQX DATAOUT High-Z tKQLZ tKQ 1a 2a 2b 2c 2d 3a tKQHZ DATAIN High-Z Pipelined Read Single Read Burst Read Unselected Integrated Circuit Solution Inc. SSR001-0B 9 IS61C632A WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter tKC tKH tKL tAS tSS tWS tDS tCES tAVS tAH tSH tDH tWH tCEH tAVH tCFG Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Configuration Setup(1) -4 Min. Max. 8 4 4 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 25 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -5 Min. Max. 10 4 4 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 35 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -6 Min. Max. 12 4 4 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 45 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -7 Min. Max. 13 6 6 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 52 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -8 Min. Max. Unit 15 6 6 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 60 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Configuration signal MODE is static and must not change during normal operation. 10 Integrated Circuit Solution Inc. SSR001-0B IS61C632A WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS ADV tAS tAH tAVH A14-A0 WR1 tWS tWH WR2 WR3 GW tWS tWH BWE tWS tWH tWS tWH BW4-BW1 tCES tCEH WR1 WR2 CE1 Masks ADSP WR3 CE1 tCES tCEH CE2 and CE3 only sampled with ADSP or ADSC Unselected with CE2 CE2 tCES tCEH CE3 OE DATAOUT High-Z tDS tDH DATAIN High-Z 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d 3a Single Write Burst Write Write Unselected Integrated Circuit Solution Inc. SSR001-0B 11 IS61C632A READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter tKC tKH tKL tKQ tKQX (2) (2,3) -4 Min. Max. 8 4 4 -- 1.5 0 1.5 -- 0 0 -- 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 25 -- -- -- 4 -- -- 4 4.5 -- -- 4.5 -- -- -- -- -- -- -- -- -- -5 Min. Max. 10 4 4 -- 1.5 0 1.5 -- 0 0 -- 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 35 -- -- -- 5 -- -- 5 4.8 -- -- 4.8 -- -- -- -- -- -- -- -- -- -6 Min. Max. 12 4 4 -- 2 0 2 -- 0 0 -- 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 45 -- -- -- 6 -- -- 6 6 -- -- 6 -- -- -- -- -- -- -- -- -- -7 Min. Max. 13 6 6 -- 2 0 2 -- 0 0 -- 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 52 -- -- -- 7 -- -- 6 6 -- -- 6 -- -- -- -- -- -- -- -- -- -8 Min. Max. Unit 15 6 6 -- 2 0 2 -- 0 0 -- 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 60 -- -- -- 8 -- -- 6 6 -- -- 6 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z tKQLZ tKQHZ(2,3) Clock High to Output High-Z tOEQ tOEQX tOELZ (2) Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z (2,3) tOEHZ(2,3) Output Disable to Output High-Z tAS tSS tWS tCES tAH tSH tWH tCEH tCFG Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Configuration Setup(1) Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with the load in Figure 2. 12 Integrated Circuit Solution Inc. SSR001-0B IS61C632A READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP tSS tSH ADSC ADV tAS tAH A14-A0 RD1 tWS tWH WR1 RD2 RD3 GW tWS tWH BWE tWS tWH BW4-BW1 tCES tCEH WR1 CE1 Masks ADSP CE1 tCES tCEH CE2 and CE3 only sampled with ADSP or ADSC CE2 tCES tCEH Unselected with CE3 CE3 tOEQ tOEHZ OE tOELZ tOEQX tKQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ 2a 2b 2c 2d tKQHZ DATAIN High-Z tDS 1a tDH Single Read Single Write Burst Read Unselected Integrated Circuit Solution Inc. SSR001-0B 13 IS61C632A SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter tKC tKH tKL tKQ tKQX (4) (4,5) -4 Min. Max. 8 4 4 -- 1.5 0 1.5 -- 0 0 -- 2.5 2.5 2.5 0.5 0.5 0.5 2 2 25 -- -- -- 4 -- -- 4 4.5 -- -- 4.5 -- -- -- -- -- -- -- -- -- -5 Min. Max. 10 4 4 -- 1.5 0 1.5 -- 0 0 -- 2.5 2.5 2.5 0.5 0.5 0.5 2 2 35 -- -- -- 5 -- -- 5 5 -- -- 4.8 -- -- -- -- -- -- -- -- -- -6 Min. Max. 12 4 4 -- 2 0 2 -- 0 0 -- 2.5 2.5 2.5 0.5 0.5 0.5 2 2 45 -- -- -- 6 -- -- 6 6 -- -- 6 -- -- -- -- -- -- -- -- -- -7 Min. Max. 13 6 6 -- 2 0 2 -- 0 0 -- 2.5 2.5 2.5 0.5 0.5 0.5 2 2 52 -- -- -- 7 -- -- 6 6 -- -- 6 -- -- -- -- -- -- -- -- -- -8 Min. Max. Unit 15 6 6 -- 2 0 2 -- 0 0 -- 2.5 2.5 2.5 0.5 0.5 0.5 2 2 60 -- -- -- 8 -- -- 6 6 -- -- 6 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc ns Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z tKQLZ tKQHZ(4,5) Clock High to Output High-Z tOEQ tOEQX tOELZ (4) Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z (4,5) tOEHZ(4,5) Output Disable to Output High-Z tAS tSS tCES tAH tSH tCEH tZZS tZZREC tCFG Address Setup Time Address Status Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Chip Enable Hold Time ZZ Standby (1) ZZ Recovery(2) Configuration Setup(3) Notes: 1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data retention is guaranteed when ZZ is asserted and clock remains active. 2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state. 3. Configuration signal MODE is static and must not change during normal operation. 4. Guaranteed but not 100% tested. This parameter is periodically sampled. 5. Tested with the load in Figure 2. 14 Integrated Circuit Solution Inc. SSR001-0B IS61C632A SNOOZE AND RECOVERY CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP ADSC ADV tAS tAH A14-A0 RD1 RD2 GW BWE BW4-BW1 tCES tCEH CE1 tCES tCEH CE2 tCES tCEH CE3 tOEQ tOEHZ OE tOELZ tOEQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ DATAIN High-Z tZZS tZZREC ZZ Single Read Snooze with Data Retention Read Integrated Circuit Solution Inc. SSR001-0B 15 IS61C632A ORDERING INFORMATION Commercial Range: 0C to +70C Speed (ns) 4 4 5 5 6 6 7 7 8 8 Order Part Number IS61C632A-4TQ IS61C632A-4PQ IS61C632A-5TQ IS61C632A-5PQ IS61C632A-6TQ IS61C632A-6PQ IS61C632A-7TQ IS61C632A-7PQ IS61C632A-8TQ IS61C632A-8PQ Package 14*20*1.4mm LQFP 14*20*2.7mm PQFP 14*20*1.4mm LQFP 14*20*2.7mm PQFP 14*20*1.4mm LQFP 14*20*2.7mm PQFP 14*20*1.4mm LQFP 14*20*2.7mm PQFP 14*20*1.4mm LQFP 14*20*2.7mm PQFP Industrial Range: -40C to +85C Speed (ns) 6 6 7 7 8 8 Order Part Number IS61C632A-6TQI IS61C632A-6PQI IS61C632A-7TQI IS61C632A-7PQI IS61C632A-8TQI IS61C632A-8PQI Package 14*20*1.4mm LQFP 14*20*2.7mm PQFP 14*20*1.4mm LQFP 14*20*2.7mm PQFP 14*20*1.4mm LQFP 14*20*2.7mm PQFP Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 16 Integrated Circuit Solution Inc. SSR001-0B |
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